1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and more particularly, to a semiconductor integrated circuit device having a test element far monitoring the process parameters of the circuit.
2. Description of the Prior Art
With a conventional semiconductor integrated circuit device, typically, a group of test elements are provided on a semiconductor chip to measure the electrical characteristics of electrical elements and/or circuits formed in the internal circuitry of the device, thereby monitoring the process parameters for the device.
The group of test elements is termed the "Test Element Group (TEG)". The TEG is laid out in a dedicated region separated from the internal circuits on the chip, which is termed the "TEG region".
A conventional semiconductor integrated circuit device of this sort is shown in FIG. 1, which is disclosed in the Japanese Non-Examined Patent Publication No. 4-365347 published in December 1992.
In FIG. 1, the reference numeral 120 indicates a TEG region, in which three transistors 122 are provided as the test elements. Each of the transistors 122 is here a three-terminal transistor. The test transistors 122 have the same configuration as that of the transistors formed in the internal circuitry of the device.
The three terminals of each transistor 122 are electrically connected to respective electrodes 121 through corresponding wiring lines 123. The three electrodes 121 are arranged to surround the corresponding transistor 122. In other words, the transistor 122 is located among the corresponding three electrodes 121.
Typically, the electrodes 121 are made of aluminum and the wiring lines 123 are made of polysilicon. The electrodes 121 are designed to have a size or area allowing the probes of a verification tester (not shown) to be contacted therewith, respectively.
Although each of the test transistors 122 is located along the corresponding three electrodes 121 in FIG. 1, the above Patent Publication No. 4-365347 discloses that it may be located below the electrodes 121 to be overlapped therewith for the purpose of reducing the chip area of the TEG region 120. Similarly, it further discloses that the wiring lines 123 may be located below the electrodes 121 to be overlapped therewith.
Additionally, bonding pads onto which bonding wires are bonded are provided on the chip separately from the TEG region 120.
A technique of arranging an electrical element or circuit below a bonding pad for the purpose of wire bonding to be overlapped therewith is disclosed in the Japanese Non-Examined Patent Publication No. 60-246668 published in December 1985.
In this technique, for example, an input/output (I/O) protection circuit for protecting the internal circuitry is arranged below the bonding pad. The I/O circuit may be formed by a diode or the combination of a diode and a resistor. There is an advantage that the input and output of the internal circuitry are protected by the protection circuit without increasing the chip area of a semiconductor integrated circuit devices
However, with the conventional semiconductor integrated circuit of FIG. 1, which is disclosed in the Japanese Non-Examined Patent Publication No. 4-365347, there is a problem that it is very difficult to decrease the chip area of the TEG region 120 itself. The reason is that each of the electrodes 121 in the TEG region 120 necessitates a specific wide area or size allowing the test probes to be in contact therewith even if the test elements 122 are miniaturized to the lower limit. This means that it is essential for the TEG region 120 to occupy a specific wide area on the chip.
On the other hand, with the technique disclosed in the Japanese Non-Examined Patent Publication No. 60-246668, there is a problem that the electrical element or circuit such as the I/O protection circuit arranged below the bonding pad may not operate normally. This is caused by the fact that the element or circuit located below the bonding pad tends to be damaged or destroyed due to the applied stress during a wire bonding process. This problem will make it impossible to use the semiconductor integrated circuit device.